In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative to the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (SDRAMs), synchronous static random access memories (SSRAMs), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device typically must be synchronized to external operations. For example, read data are placed on a data bus by the memory device in synchronism with an external clock signal. The memory device must latch and drive the data onto the data bus at the proper times to successfully provide the read data. To latch the read data and drive it onto the data bus, an internal clock signal is developed in response to the external clock signal, and is typically applied to the data latches and data drivers contained in the memory device to thereby clock the data onto the data bus. The internal clock signal and external clock must be synchronized to ensure the internal clock signal clocks the latches and data drivers at the proper times to successfully provide the read data. In the present description, “external” is used to refer to signals and operations outside of the memory device, and “internal” to refer to signals and operations within the memory device. Moreover, although the present description is directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.
Internal circuitry in the memory device that generates the internal clock signal necessarily introduces some time delay, causing the internal clock signal to be phase shifted relative to the external clock signal. As long as the phase-shift is minimal, timing within the memory device can be easily synchronized to the external timing. To increase the rate at which commands can be applied and at which data can be transferred to and from the memory device, the frequency of the external clock signal is increased, and in modern synchronous memories the frequency is in excess of 500 MHz. As the frequency of the external clock signal increases, however, the time delay introduced by the internal circuitry becomes more significant. This is true because as the frequency of the external clock signal increases, the period of the signal decreases and thus even small delays introduced by the internal circuitry correspond to significant phase shifts between the internal and external clock signals. As a result, the commands applied to the memory device may no longer be valid by the time the internal clock signal clocks the latches. Additionally, as the frequency of the external clock increases, variations in the duty cycle of the clock signal introduce a greater duty cycle error. An ideal duty cycle for a clock signal is typically 50 percent. That is, over the period of a clock cycle, the clock signal is HIGH for 50 percent of the period. As the period of the clock signals become shorter due to the increased clock frequency, a clock variation that results in a subtle shift in duty cycle, and which can be ignored at a lower clock frequency, may result in a much more significant shift in the duty cycle of the higher frequency clock signal. In some instances, if the duty cycle of the clock signal is left uncorrected, timing errors may cause the memory device to fail.
To synchronize external and internal clock signals in modern synchronous memory devices, a number of different approaches have been considered and utilized, including delay-locked loops (DLLs), as will be appreciated by those skilled in the art. As used herein, the term synchronized includes signals that are coincident and signals that have a desired delay relative to one another. To correct duty cycle errors in clock signals, duty cycle correction (DCC) circuits are used to generate clock signals having a 50 percent duty cycle. FIG. 1 illustrates a conventional clock generator 100 having a DLL 110 and a DCC circuit 120. An input clock signal CLK represents an external clock signal applied to the DLL. As will be explained in more detail below, the DLL generates an output clock signal CLK0 that is synchronized with the CLK signal. Due to the design of conventional DLLs, a duty cycle error in the CLK signal will be carried through to the CLK0 signal. Thus, the CLK0 signal is provided to the DCC 120 to correct any duty cycle error and generate an output clock signal CLKSYNC that is synchronized with the CLK0 signal and has a duty cycle corrected to 50 percent.
FIG. 2 illustrates the conventional DLL 110 and the DCC circuit 120 in greater detail. The DLL includes an input buffer 202 that provides a buffered clock signal CLKBUF in response to receiving the CLK signal. The CLKBUF signal is delayed relative to the CLK signal due to a propagation delay of the input buffer 202. The CLKBUF signal is provided to a variable delay circuit 204 that has a variable delay Td controlled by an adjustment signal DADJ1 generated by a shift register 206. The output clock signal of the variable delay is the CLK0 signal, which is delayed relative to the CLKBUF signal by the variable delay Td. An output clock signal CLKSYNC is fed back through a model delay 208 to provide a feedback clock signal CLKFB1. The model delay 208 adds a delay Tm to the CLKSYNC signal, which is approximately equal to the total delay of the input buffer 202, an output buffer 240, which is included in the DCC 120, and delay that is injected by the DCC 120 to the CLK0 signal and a CLK180 signal. A phase detector compares the CLKBUF and CLKFB1 signals, and generates a control signal DCONT1 for the shift register 206 in response to the phase difference between the CLKBUF and CLKFB1 signals. The variable delay circuit 204 is adjusted until the variable delay Td is sufficient to synchronize the CLKBUF and CLKFB1 signals. When the CLKBUF and CLKFB1 signals are in phase, the DLL 110 is said to be “locked.” Under this condition, the timing of the CLK0 signal is such that the delay of the output buffer 240 is accommodated, and a clock signal output by the output buffer 240 would be in phase with the CLK signal. As known in the art, when the CLKBUF and CLKFB1 signals are in phase, the delay of the DLL feedback loop, generally defined by the variable delay 204 and the model delay 208, is a multiple of the period TCLKBUF of the CLKBUF signal. That is, the feedback loop delay is equal to n*TCLKBUF, where “n” is an integer value.
As previously mentioned, the CLK0 signal is provided to the DCC circuit 120 for duty cycle correction. The DCC circuit 120 includes a first variable delay 230 and a second variable delay 232, which are coupled in series. An output clock signal CLKFB2 of the variable delay 232 is compared with the CLK0 signal by a phase detector 238. The phase detector 238 generates a control signal DCONT2 that is provided to a shift register 234. The shift register 234 generates an adjustment signal DADJ2 based on the DCONT2 signal that is used to adjust both the variable delay 230 and the variable delay 232 to the same delay. When the variable delays 230, 232 have been adjusted so that the phase difference between the CLK0 and CLKFB2 signals is an odd multiple of the clock period of the CLK0 signal an output clock signal CLK180 from the first variable delay 230 is 180 degrees out of phase from the CLK0 signal. As known in the art, the delay of the feedback loop for the DCC 120, which is generally defined by the variable delays 230 and 232, is equal to one period of the CLK0 signal. Thus, one-half the loop delay, that is, the delay of one of the variable delays 230 or 232, will provide a delay equal to one-half the period of the CLK0 signal, which is a clock signal 180 degrees out of phase from the CLK0 signal. The CLK0 and CLK180 signals are used by the output buffer 240 to generate the CLKSYNC signal, which is synchronized with the CLK signal and has a corrected duty cycle.
Although the clock generator 100 provides a synchronized clock signal having a corrected duty cycle, the circuit is slow to generate the CLKSYNC signal upon startup and is cumbersome. The conventional clock generator 100 is slow because two different feedback loops must be locked before an acceptable CLKSYNC signal is generated. That is, upon start up, the DCC 120 must be synchronized before the DLL 110 is activated to provide a clock signal having the appropriate delay relative to the CLK signal or the DLL 110 is synchronized before the DCC 120 is activated for duty cycle correction. In the event the DLL 110 is synchronized before the DCC 120 is activated, the time required to generate a synchronized CLK0 signal can take several hundred clock cycles. The DCC 120 then takes additional time for it to adjust the variable delays 230 and 234 to synchronize the CLK0 signal and the CLKFB signal to provide a suitable CLK180 signal. The time for the DCC 120 to lock can add a significant amount of time to the already lengthy time it takes to lock the DLL 110. The clock generator 100 is cumbersome because the circuit includes nearly two complete DLLs. That is, the clock generator 100 includes three different variable delay circuits 204, 230, 232, two phase detectors 210, 238, and two shift registers 206, 234. A variable delay typically takes up a relatively large amount of space on a semiconductor substrate on which the clock generator and other components of a memory device are formed. Having multiple variable delays only exacerbates the issue and can be undesirable where the general design goal is reducing circuit size. Moreover, a variable delay has relatively high power consumption, which may be particularly undesirable in low-power applications, such as in a portable battery-operated device. Having multiple variable delays only increases power consumption, making a potentially undesirable situation even worse.
Therefore, there is a need for an alternative clock generator that combines the functions of a DLL and DCC circuit and reduces the number of redundant circuits.